Oct 04, 2017 term paper 2

3. S T UD Y SECTION 16 . 4 , DESIGN OF SEQUENTIAL CIRCUITS USING ROMS AND PLAS . (A) REVIE W…

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3. Study Section 16. 4,Design of Sequential Circuits Using ROMs and PLAs.

(a) Review Section 9. .5,Read -Only Memories, and Section 9. 6,Progra mmable Logic Devices.

(b) v1hat size ROM would be required to realize a state tablewith 13 states, two input variables, and three output variables?

(c) In going from Table 16-6(b) to 16-6(c), note that for X = o, Q1:

(d) 2Q3:

(e) = ooo,Z = 1, and Q1:

(f) Q2:

(g) Q3:

(h) = D1D2D3 = 001; therefore, 1001is entered in the first row of the truth table.Verify that the other truth table entries are correct.

(i) Continue the analysis of the PLA realization of the code converter which was started in the paragraph following Table 16-7. In particular, if

Q1:

2Q3:

= 100 and X = 1,what willbe the PLA outputs? vVhat will the statebe after the clock?

(j) .Vork Problems 16.1.5 and 16.16.


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